The present invention relates to telecommunication networks, and more particularly to the reduction of transients in a clock generating system.
A telecommunication network basically comprises switches S or equivalents, physical links interconnecting said switches, and various auxiliary devices (FIG. 1). Normally, a telecommunication system would be implemented with more switches and trunk groups than is illustrated in FIG. 1. However, for simplicity, the present invention will be explained using the simplified representations of FIG. 1. A switch S generally comprises a number of circuits, both analog and digital circuits, which are mounted on circuit boards that are stored in cabinets. A physical link utilizes transmission equipment, such as fiber optic conductors, coaxial cables or radio links. In general, physical links are grouped into trunk groups TG which extend between said switches. There are access points to the physical network, to which access points, access units such as telephone sets and computer modems, are connected.
A switch S normally includes a clock generating system which provides the digital circuits in the switch with clock signals. To meet the requirements on safety and reliability and to increase the mean time between system failure (MTBSF), the clock generating system should be redundant. Redundancy in the clock generating system is ensured by using multiple clock generating units. The unit which generates the clock signal is manifold; usually duplicated or triplicated. These units or boards are referred to as clock signal generating planes.
In general, the clock generating system can be of the type master-slave or a mutually regulating clock generating system. In a clock generating system of the type master-slave, one clock signal generating plane acts master, and the clock signals of the other clock signal generating planes, the slaves, are normally synchronized to the clock signal of the master plane. In a mutually regulating clock system, all the clock signal generating planes are synchronized with each other in frequency as well as in phase. The synchronization between the clock signal generating planes is generally effectuated by a regulation system. Since the clock signals of all the planes are regulated towards each other, the regulation is referred to as mutual regulation.
A mutually regulating clock system has a natural readiness or preparedness when a malfunction occurs or when a plane in the clock system is pulled out from a cabinet. If, in a master-slave type of clock system, a fault or malfunction occurs in the master, a reconfiguration has to be performed quickly. The administration of this reconfiguration is a difficulty that is avoided in a mutual clock system. A mutual regulation between the planes makes it possible to have identical planes regarding both hardware as well as software. In the following, what is generally under consideration is a mutually regulating clock generating system.
The clock signal generating planes should also be synchronized with an external reference signal. This is referred to as network synchronization. If the switch is not synchronized to incoming data, slip may occur in the transmission and data will be lost. Disruptions in a data stream entering a switch which are generally caused by underflows or overflows are referred to as slips. Another reason for having network synchronization is that the output clock signal of one switch can act as reference clock signal to another switch. In this way, many switches may be connected in cascade.
When a switch is synchronized with the network reference, the requirements on how the phase of the clock signal of the switch may change in relation to the phase of the reference clock signal input to the switch, are high. The transfer function of a switch from input signal to output signal is standardized. There is also a measure called MRTIE (Maximum Relative Time Interval Error) which specifies how much the phase of the clock signal output from the switch may change in relation to the phase of the reference clock signal input to the switch, over a certain period of time. Other measures of the clock signal quality also exist.
If a clock generating plane is excluded from the clock system due to the actions of an operator or because of a malfunction, or if a plane is plugged into and subsequently included into the clock system, a reconfiguration of the clock system takes place. More precisely, an exclusion of a clock generating plane from the mutual regulation of the clock system, or an inclusion of a further plane into the mutual regulation of the clock system is referred to as a reconfiguration of the mutually regulating clock system. This kind of reconfiguration of the system may change the frequency for the whole system of mutually regulating planes; a transient will be introduced into the clock system. This transient will normally generate unacceptably large phase differences between the clock signal of the switch and the reference signal, which, in turn, will create transmission slip so that data will be lost. This is particularly so, when the filter circuit or regulator in the clock generating planes includes an amplifying unit, such as a proportionally amplifying block (by way of example: the proportional path P of a PI- or PID-regulator).
Normally, a similar problem is encountered in a mutually regulating clock system when the network synchronization is activated. When the clock signal generating planes of the mutually regulating clock system start to synchronize to a network reference signal, transients may be introduced into the clock system.
It is the provision of methods for reducing transients in a clock generating system to which the present invention is directed.